Non-volatile memory (NVM) devices typically are composed of a matrix of bit cells, with each bit cell storing a corresponding bit of data. Each bit cell generally is configured as one or more transistors capable of storing electrons as charge, and thereby affecting the relationship between the control electrode voltage and the drain current of the transistor. The transistor is “erased” to one state (e.g., a logic “1”) by clearing the charge and the transistor is “programmed” to another state (e.g., a logic “0”) by storing charge at the transistor. Thus, the bit value “stored” by the transistor can be sensed by comparing a reference (either a current or a voltage) to the drain current of the transistor in response to the application of a read voltage to the control electrode of the transistor, whereby the “stored” value is determined to be one state (e.g., a logic “1” or an “erased” state) if the drain current is greater than the read reference and determined to be another state (e.g., a logic “0” or a “programmed” state) if the drain current is less than the read reference.
Some NVM architectures utilize an insulating element, such as a thin film nitride layer or a nanocrystal layer, at the transistor. These architectures typically offer reduced production costs compared to other types architectures due to reduced silicon area, fewer processing steps and generally higher yields. However, for many thin film architectures and similar architectures, the insulating element exhibits a “trap-up” characteristic over numerous program/erase cycles whereby the insulating element becomes saturated with charge, thereby increasing the threshold voltage (Vt) of the bit cell and consequently decreasing the drain current of the bit cell in response to the same control electrode voltage. Accordingly, if a fixed read reference is used, increasing trap-up of the bit cell eventually will cause an erroneous read of the bit cell due to the decreasing drain current in comparison to the fixed read reference. In many applications, this erroneous read is unacceptable.
Conventional read reference adjustment techniques have been developed to attempt to overcome the trap-up characteristics of NVM bit cells. One conventional technique includes the use of a reference transistor that is used to generate the read reference based on the assumption that the reference transistor will exhibit the same trap up characteristics as the bit cell. This approach typically entails subjecting the reference transistor to the same program/erase cycles in accordance with the bit cells it is attempting to emulate. Another conventional technique uses a fixed reference current. In this approach, design considerations must be made to account for end-of-life cell characteristics that force a larger operating window at beginning-of-life, increase power consumption, as well as force non-optimum design choices. Accordingly, an improved technique for adjusting the read reference for a NVM device would be advantageous.
The use of the same reference symbols in different drawings indicates similar or identical items.